1. Field of the Invention
The present invention relates to a power MOSFET, in particular, a vertical-type power MOSFET (referred to as “power MOSFET”, hereinafter) having a gate formed in a trench, which is generally used with a breakdown voltage of 100V or less.
2. Description of the Related Art
Recently, the use of the power MOSFET has greatly increased not only in the market for large-current, high-breakdown voltage switching power supply but also in the market for energy saving switches for mobile communication apparatuses such as note type personal computers. The power MOSFET is applied to a power management circuit or a safety circuit of a lithium ion battery. Thus, the power MOSFET is exceedingly desired to attain low voltage operation, which makes it possible to directly drive the MOSFET with battery voltage, and low ON-state resistance.
Conventionally, the power MOSFET of this type has a structure as shown in FIG. 9. FIG. 9 is a cross-sectional view showing the structure of a unit cell part of the conventional n-channel MOSFET. In the trench gate MOSFET, an n− type drift layer 102 is formed on a first main surface of an n+ type silicon substrate 101 as an n+ type drain layer, to have the thickness of 2.0 μm, for example. A p type base layer 103 is formed on the n− type drift layer 102. In the p type base layer 103 and the n− type drift layer 102, a plurality of trenches 104 are formed at predetermined intervals to have the depth of passing through the p type base layer 103 and extending into the n− type drift layer 102 with a predetermined depth.
In the trench 104, gate electrodes 106 are buried with gate insulating films 105, for example, having the thickness of 25 nm intervening therebetween.
In the surface region of the p type base layer 103, a pair of n+ type source layers 107 are formed by a selective impurity diffusion method adjacent to the gate insulating films 105 formed in the trench 104. In addition, in the surface region of the p type base layer 103 between the pair of the n+ type source layers 107, a p+ type layer 108 is formed by the selective impurity diffusion method. A source electrode 109 is formed to come into contact with both the pair of n+ type source layers 107 and the p+ type layer 108. On the second main surface of the n+ type silicon substrate 101, opposite side to the n− type drift layer 102, a drain electrode 110 is provided.
In the MOSFET having a structure described above, ON resistance of the device is determined mainly by channel resistance in the p type base layer 103 and resistance of the drift layer 102. Therefore, in the past, when the width of the unit cell, denoted by w in FIG. 9, is reduced, channel density on the silicon substrate 101 has been increased. As a result, the ON resistance of the power MOSFET device has been reduced.
However, in recent years, miniaturization of the device has been improved with the progress of manufacturing process, so that the width w of the unit cell has been reduced. Accordingly, the channel density has been increased, and thus two third of the entire ON resistance in the MOSFET device is occupied with resistance of the aforementioned drift layer 102. Therefore, a problem arises, even if technique of miniaturizing is improved so as to reduce the width w of the unit cell, the ON resistance cannot be reduced remarkably. For example, in a 30V (breakdown voltage) type of power MOSFET, it is very difficult to reduce. the ON resistance to 20 mΩ.mm2 or less.
To solve the above problem, as shown in FIG. 10, there has been proposed a power MOSFET having the structure in that the thickness of the drift layer 120 is reduced by forming gate insulating films 125 to be thick, so that resistance of the drift layer 120 is reduced.
More specifically, as shown in FIG. 10, the n− type drift layer 120 and the p type base layer 103 are formed on the n+ type silicon substrate 101, and a plurality of trenches 104 are formed in the p type base layer 103 and the n− type drift layer 102. The plurality of trenches 104 are formed from the p type base layer 103 into the n− type drift layer 120.
In the trenches 104, the gate electrodes 106 are buried in the trenches 104 with the gate insulating film 125, whose film is thick, intervening therebetween. In the surface region of the p type base layer 103, a pair of n+ type source layers 107 are selectively formed by selectively diffusing impurities adjacent to the thick gate insulating films 125 formed on an inner wall of the trenches 104. In addition, the p+ type layer 108 is formed between the pair of n+ type source layers 107 by selectively diffusing impurities. The source electrode 109 is formed to be in contact with both the n+ type source layers 107 and the p+ type layer 108. On the second main surface of the n+ type silicon substrate 101, opposite side to the n− type drift layer 102, the drain electrode 110 is provided.
The gate insulating film 125 is formed to be thick, i.e., to have the thickness of 100 nm as compared with the thickness of 25 nm in the case of the power MOSFET shown in FIG. 9. By making the gate insulating film 125 to share voltage to be applied between the gate electrode 106 and the drain electrode 110, the thickness of the n− type drift layer 120 is formed to be thin, i.e., 0.5 μm as compared with the thickness of 2.0 μm in the power MOSFET shown in FIG. 9, thereby reducing the resistance of the n− type drift layer 120.
However, in this power MOSFET device, the following problem arises. That is, in a case where the gate insulating films 125 are simply formed to be thick and the thickness of the drift layer 120 intervening between the gate insulating films 125 and the n+ substrate 101 is formed to be thin as shown in FIG. 10, the resistance of the drift layer 120 can be reduced, however, the threshold voltage of the channel increases by contraries. Thus, the channel resistance is increased in applying the same gate voltage as before. For this reason, it is difficult to reduce the entire ON resistance over the device.
As described above, in any one of the conventional power MOSFETs shown in FIG. 9 and FIG. 10, there has been a problem in that the ON resistance cannot be reduced while miniaturizing the device.